The present invention relates to data processing systems and more particularly relates to apparatus for controlling peripheral devices associated with data processing systems.
One object of the present invention is the optimizing of the execution of several microprocesses in a multiprogrammed system for the processing of data.
In data processing systems, it is classical to use an input-output control program, or channel program, to define the types of transfers which must take place between the central processing unit and a peripheral device. When the program which is being executed has an input-output operation to perform, the instruction indicates the address of the peripheral device on which the operation must be performed, as well as the address of the corresponding channel program or control address. The address of the peripheral device and the control address are transferred into an input-output register. The address of the peripheral device is transmitted on a bus which connects the peripheral devices to the central unit; the peripheral device recognizes its own address and responds to the central unit by indicating its state. If the peripheral device is not available, the control data and the peripheral device number are stored into a queue to be referred to again a moment later. If the peripheral device is available, a connection is established and the transfer of data is initiated. The channel program is commenced and the execution of each order takes place as called for by the peripheral device, until the last order has been executed. The initialization of a transfer of data may take place in the other direction. In this case, the peripheral devices request an order. The central unit determines, among all order requests, the one which has the highest priority. Once that stage has been completed, the connection between the peripheral device having the highest priority and the central unit takes place. The peripheral device then sends a transfer request indicating whether the transfer is input or output. The transfer then is executed and it may or may not be followed by other transfers. The end of the exchanges is indicated by an end of order request messages.
In a multiprogrammed data processing system which has several peripheral devices, the linking of the input-output operations is done by means of interrupt messages. The interrupt normal occurs at the end of the execution of a task on a peripheral device, but there may be other causes for interrupts. When an interrupt message is detected, it is usual for the operating system to examine the active microprocesses which are ready to be executed. The system then gives transfer control to the microprocess which has the highest priority over the other microprocesses to be executed, and so forth. A system exists whereby low priority microprocesses are given control when these microprocesses have been queuing for execution for a long enough period of time.
By using channel programs in processing devices, the central unit becomes completely independent of peripheral device management. However, the channel programs themselves do not enable the simultaneous management of several peripheral devices, but require the completion of microprocesses one-at-a-time. Certain peripheral devices may have to queue for a considerable period of time before being granted control of the corresponding channel program; this usually occurs for slow peripherals.
The present invention has as one purpose the creation of a mechanism which, from an overall point of view, makes possible the simultaneous control of the microprocesses. In other words, the invention renders transparent the link between the central unit and the various peripheral devices.
The present invention provides an organization of a data processing system which is multiprogrammed, which includes a central processing unit (CPU) connected to peripheral control units PCU, in which each peripheral control unit works as a master mode with respect to the central unit and to the peripheral devices in order to increase the processing capacity of the central unit, and in which the connection between the central unit and the peripheral devices through a peripheral control unit is transparent enough so that the execution of the various microprocesses by the peripheral control unit is simultaneous. As a result, the microprocesses are distributed in a judicious manner both in space and in time. Distribution in space takes place in suitable memory fields; the distribution over time is obtained by defining specific times of initiating and linking the microprocesses among themselves when an interruption occurs or when a microprocess has been completed. In order to achieve those ends, the present invention provides the PCU with a "Firmware".
The "Firmware" includes a set of microprograms, and of tables or Micro-operating systems (MIOS) which coordinate and render optimum the operations in the PCU. The firmware also includes a set of microprograms and of tables to control the peripheral devices. The microprograms which constitute the MIOS control a multiprogrammed clock, the treatment of the interruptions of the hardware, and the control of the microprocesses for the purpose of their execution. The whole of the microprograms and the tables necessary for the control of a group of homogeneous peripheral devices, such as a group of card readers of different types, will be designated by the term "Attachment firmware package" (AFP). There exists a version of Firmware suitable for each particular configuration of peripheral devices attached to the PCU and each version of Firmware works under the supervision of the MIOS. An AFP executes the orders elaborated by the MIOS or by the channel programs (through the MIOS) and takes into account the signals of the peripheral devices. The AFP contains the following elements:
1. One or several control blocks (DACB) of peripheral device adaptors (DA). Each DACB defines the space of data and the space of microprograms in memory, that is, all of the resources assigned to the AFP to control the peripheral devices connected to the peripheral device adaptors. PA1 2. A group of control blocks (MCB) of microprocesses. Each MCB controls a microprocess which will be activated to execute the specific functions of the attachment. PA1 3. A group of microprograms. The micro-programs may be re-entering, so as to facilitate their division into several microprocesses. PA1 4. Data fields which contain either permanent or transient data relative to the various microprocesses of the AFP.
A microprocess is a series of microprogrammed operations which when executed, generate a sequence of microinstructions without simultaneity; within the framework of this specification, a microprocess appears as the potential execution, by means of microinstructions, of asynchronous specific functions under the control of an AFP. Microinstructions corresponding to a microprocess are "running" when the microinstructions are being executed. A microprocess is "activated" when the microinstructions corresponding to the microprocess are running. A microprocess may be activated either by the MIOS at the time of appearance of one or several specific events, or at the call of an AFP. A microprocess may belong to one or to the other of the following two classes. The first class is composed of the microprocesses called EV1 and EV2 which have the properties of being automatically initiated at the start of events called EV1 and EV2 (i.e., at the notification of events No. 1 and No. 2), and of being nonaddressable by other microprocesses. That is, the other microprocesses cannot have any affect on them. The second class is called the class of ordinary microprocesses. The ordinary microprocesses can be addressed by other microprocesses by means of control blocks (MCB) of associated microprocesses. The name of an ordinary microprocess is defined by the address of its MCB. The name of each MCB is known to AFP; it has been defined at the time of the assembling (See Glossary for definition).